Crypto++ 7.0 Free C++ class library of cryptographic schemes

cpu.h
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1 // cpu.h - originally written and placed in the public domain by Wei Dai
2 // updated for ARM and PowerPC by Jeffrey Walton.
3 // updated to split CPU_Query() and CPU_Probe() by Jeffrey Walton.
4
5 /// \file cpu.h
6 /// \brief Functions for CPU features and intrinsics
7 /// \details The CPU functions are used in IA-32, ARM and PowerPC code paths. The
8 /// functions provide cpu specific feature testing on IA-32, ARM and PowerPC machines.
9 /// \details Feature detection uses CPUID on IA-32, like Intel and AMD. On other platforms
10 /// a two-part strategy is used. First, the library attempts to *Query* the OS for a feature,
11 /// like using Linux getauxval() or android_getCpuFeatures(). If that fails, then *Probe*
12 /// the cpu executing an instruction and an observe a SIGILL if unsupported. The general
13 /// pattern used by the library is:
14 /// <pre>
15 /// g_hasCRC32 = CPU_QueryCRC32() || CPU_ProbeCRC32();
16 /// g_hasPMULL = CPU_QueryPMULL() || CPU_ProbePMULL();
17 /// g_hasAES = CPU_QueryAES() || CPU_ProbeAES();
18 /// </pre>
19 /// \details Generally speaking, CPU_Query() is in the source file <tt>cpu.cpp</tt> because it
20 /// does not require special architectural flags. CPU_Probe() is in a source file that recieves
21 /// architectural flags, like <tt>sse_simd.cpp</tt>, <tt>neon_simd.cpp</tt> and
22 /// <tt>ppc_simd.cpp</tt>. For example, compiling <tt>neon_simd.cpp</tt> on an ARM64 machine will
23 /// have <tt>-march=armv8-a</tt> applied during a compile to make the instruction set architecture
24 /// (ISA) available.
25 /// \details The cpu probes are expensive when compared to a standard OS feature query. The library
26 /// also avoids probes on Apple platforms because Apple's signal handling for SIGILLs appears to
27 /// corrupt memory. CPU_Probe() will unconditionally return false for Apple platforms. OpenSSL
28 /// experienced the same problem and moved away from SIGILL probes on Apple.
29
30 #ifndef CRYPTOPP_CPU_H
31 #define CRYPTOPP_CPU_H
32
33 #include "config.h"
34
35 // Issue 340
36 #if CRYPTOPP_GCC_DIAGNOSTIC_AVAILABLE
37 # pragma GCC diagnostic push
38 # pragma GCC diagnostic ignored "-Wconversion"
39 # pragma GCC diagnostic ignored "-Wsign-conversion"
40 #endif
41
42 // Applies to both X86/X32/X64 and ARM32/ARM64
43 #if defined(CRYPTOPP_LLVM_CLANG_VERSION) || defined(CRYPTOPP_APPLE_CLANG_VERSION)
44 #define NEW_LINE "\n"
45 #define INTEL_PREFIX ".intel_syntax;"
46 #define INTEL_NOPREFIX ".intel_syntax;"
47 #define ATT_PREFIX ".att_syntax;"
48 #define ATT_NOPREFIX ".att_syntax;"
49 #elif defined(__GNUC__)
50 #define NEW_LINE
51 #define INTEL_PREFIX ".intel_syntax prefix;"
52 #define INTEL_NOPREFIX ".intel_syntax noprefix;"
53 #define ATT_PREFIX ".att_syntax prefix;"
54 #define ATT_NOPREFIX ".att_syntax noprefix;"
55 #else
56 #define NEW_LINE
57 #define INTEL_PREFIX
58 #define INTEL_NOPREFIX
59 #define ATT_PREFIX
60 #define ATT_NOPREFIX
61 #endif
62
63 #ifdef CRYPTOPP_GENERATE_X64_MASM
64
65 #define CRYPTOPP_X86_ASM_AVAILABLE
66 #define CRYPTOPP_BOOL_X64 1
67 #define CRYPTOPP_SSE2_ASM_AVAILABLE 1
68 #define NAMESPACE_END
69
70 #else
71
72 NAMESPACE_BEGIN(CryptoPP)
73
74 // ***************************** IA-32 ***************************** //
75
76 #if CRYPTOPP_BOOL_X86 || CRYPTOPP_BOOL_X32 || CRYPTOPP_BOOL_X64 || CRYPTOPP_DOXYGEN_PROCESSING
77
78 #define CRYPTOPP_CPUID_AVAILABLE 1
79
80 // Hide from Doxygen
81 #ifndef CRYPTOPP_DOXYGEN_PROCESSING
82 // These should not be used directly
83 extern CRYPTOPP_DLL bool g_x86DetectionDone;
84 extern CRYPTOPP_DLL bool g_hasSSE2;
85 extern CRYPTOPP_DLL bool g_hasSSSE3;
86 extern CRYPTOPP_DLL bool g_hasSSE41;
87 extern CRYPTOPP_DLL bool g_hasSSE42;
88 extern CRYPTOPP_DLL bool g_hasAVX;
89 extern CRYPTOPP_DLL bool g_hasAVX2;
90 extern CRYPTOPP_DLL bool g_hasAESNI;
91 extern CRYPTOPP_DLL bool g_hasCLMUL;
92 extern CRYPTOPP_DLL bool g_hasSHA;
93 extern CRYPTOPP_DLL bool g_hasADX;
94 extern CRYPTOPP_DLL bool g_isP4;
95 extern CRYPTOPP_DLL bool g_hasRDRAND;
96 extern CRYPTOPP_DLL bool g_hasRDSEED;
97 extern CRYPTOPP_DLL bool g_hasPadlockRNG;
98 extern CRYPTOPP_DLL bool g_hasPadlockACE;
99 extern CRYPTOPP_DLL bool g_hasPadlockACE2;
100 extern CRYPTOPP_DLL bool g_hasPadlockPHE;
101 extern CRYPTOPP_DLL bool g_hasPadlockPMM;
102 extern CRYPTOPP_DLL word32 g_cacheLineSize;
103
104 CRYPTOPP_DLL void CRYPTOPP_API DetectX86Features();
105 CRYPTOPP_DLL bool CRYPTOPP_API CpuId(word32 func, word32 subfunc, word32 output[4]);
106 #endif // CRYPTOPP_DOXYGEN_PROCESSING
107
108 /// \name IA-32 CPU FEATURES
109 //@{
110
111 /// \brief Determines SSE2 availability
112 /// \returns true if SSE2 is determined to be available, false otherwise
113 /// \details MMX, SSE and SSE2 are core processor features for x86_64, and
114 /// the function always returns true for the platform.
115 /// \note This function is only available on Intel IA-32 platforms
116 inline bool HasSSE2()
117 {
118 #if CRYPTOPP_BOOL_X64
119 return true;
120 #else
121 if (!g_x86DetectionDone)
122 DetectX86Features();
123 return g_hasSSE2;
124 #endif
125 }
126
127 /// \brief Determines SSSE3 availability
128 /// \returns true if SSSE3 is determined to be available, false otherwise
129 /// \details HasSSSE3() is a runtime check performed using CPUID
130 /// \note This function is only available on Intel IA-32 platforms
131 inline bool HasSSSE3()
132 {
133 if (!g_x86DetectionDone)
134 DetectX86Features();
135 return g_hasSSSE3;
136 }
137
138 /// \brief Determines SSE4.1 availability
139 /// \returns true if SSE4.1 is determined to be available, false otherwise
140 /// \details HasSSE41() is a runtime check performed using CPUID
141 /// \note This function is only available on Intel IA-32 platforms
142 inline bool HasSSE41()
143 {
144 if (!g_x86DetectionDone)
145 DetectX86Features();
146 return g_hasSSE41;
147 }
148
149 /// \brief Determines SSE4.2 availability
150 /// \returns true if SSE4.2 is determined to be available, false otherwise
151 /// \details HasSSE42() is a runtime check performed using CPUID
152 /// \note This function is only available on Intel IA-32 platforms
153 inline bool HasSSE42()
154 {
155 if (!g_x86DetectionDone)
156 DetectX86Features();
157 return g_hasSSE42;
158 }
159
160 /// \brief Determines AES-NI availability
161 /// \returns true if AES-NI is determined to be available, false otherwise
162 /// \details HasAESNI() is a runtime check performed using CPUID
163 /// \since Crypto++ 5.6.1
164 /// \note This function is only available on Intel IA-32 platforms
165 inline bool HasAESNI()
166 {
167 if (!g_x86DetectionDone)
168 DetectX86Features();
169 return g_hasAESNI;
170 }
171
172 /// \brief Determines Carryless Multiply availability
173 /// \returns true if pclmulqdq is determined to be available, false otherwise
174 /// \details HasCLMUL() is a runtime check performed using CPUID
175 /// \since Crypto++ 5.6.1
176 /// \note This function is only available on Intel IA-32 platforms
177 inline bool HasCLMUL()
178 {
179 if (!g_x86DetectionDone)
180 DetectX86Features();
181 return g_hasCLMUL;
182 }
183
184 /// \brief Determines SHA availability
185 /// \returns true if SHA is determined to be available, false otherwise
186 /// \details HasSHA() is a runtime check performed using CPUID
187 /// \since Crypto++ 6.0
188 /// \note This function is only available on Intel IA-32 platforms
189 inline bool HasSHA()
190 {
191 if (!g_x86DetectionDone)
192 DetectX86Features();
193 return g_hasSHA;
194 }
195
196 /// \brief Determines ADX availability
197 /// \returns true if ADX is determined to be available, false otherwise
198 /// \details HasADX() is a runtime check performed using CPUID
199 /// \since Crypto++ 7.0
200 /// \note This function is only available on Intel IA-32 platforms
201 inline bool HasADX()
202 {
203 if (!g_x86DetectionDone)
204 DetectX86Features();
205 return g_hasADX;
206 }
207
208 /// \brief Determines AVX availability
209 /// \returns true if AVX is determined to be available, false otherwise
210 /// \details HasAVX() is a runtime check performed using CPUID
211 /// \since Crypto++ 7.1
212 /// \note This function is only available on Intel IA-32 platforms
213 inline bool HasAVX()
214 {
215 if (!g_x86DetectionDone)
216 DetectX86Features();
217 return g_hasAVX;
218 }
219
220 /// \brief Determines AVX2 availability
221 /// \returns true if AVX2 is determined to be available, false otherwise
222 /// \details HasAVX2() is a runtime check performed using CPUID
223 /// \since Crypto++ 7.1
224 /// \note This function is only available on Intel IA-32 platforms
225 inline bool HasAVX2()
226 {
227 if (!g_x86DetectionDone)
228 DetectX86Features();
229 return g_hasAVX2;
230 }
231
232 /// \brief Determines if the CPU is an Intel P4
233 /// \returns true if the CPU is a P4, false otherwise
234 /// \details IsP4() is a runtime check performed using CPUID
235 /// \note This function is only available on Intel IA-32 platforms
236 inline bool IsP4()
237 {
238 if (!g_x86DetectionDone)
239 DetectX86Features();
240 return g_isP4;
241 }
242
243 /// \brief Determines RDRAND availability
244 /// \returns true if RDRAND is determined to be available, false otherwise
245 /// \details HasRDRAND() is a runtime check performed using CPUID
246 /// \note This function is only available on Intel IA-32 platforms
247 inline bool HasRDRAND()
248 {
249 if (!g_x86DetectionDone)
250 DetectX86Features();
251 return g_hasRDRAND;
252 }
253
254 /// \brief Determines RDSEED availability
255 /// \returns true if RDSEED is determined to be available, false otherwise
256 /// \details HasRDSEED() is a runtime check performed using CPUID
257 /// \note This function is only available on Intel IA-32 platforms
258 inline bool HasRDSEED()
259 {
260 if (!g_x86DetectionDone)
261 DetectX86Features();
262 return g_hasRDSEED;
263 }
264
265 /// \brief Determines Padlock RNG availability
266 /// \returns true if VIA Padlock RNG is determined to be available, false otherwise
267 /// \details HasPadlockRNG() is a runtime check performed using CPUID
268 /// \note This function is only available on Intel IA-32 platforms
269 inline bool HasPadlockRNG()
270 {
271 if (!g_x86DetectionDone)
272 DetectX86Features();
273 return g_hasPadlockRNG;
274 }
275
276 /// \brief Determines Padlock ACE availability
277 /// \returns true if VIA Padlock ACE is determined to be available, false otherwise
278 /// \details HasPadlockACE() is a runtime check performed using CPUID
279 /// \note This function is only available on Intel IA-32 platforms
280 inline bool HasPadlockACE()
281 {
282 if (!g_x86DetectionDone)
283 DetectX86Features();
284 return g_hasPadlockACE;
285 }
286
287 /// \brief Determines Padlock ACE2 availability
288 /// \returns true if VIA Padlock ACE2 is determined to be available, false otherwise
289 /// \details HasPadlockACE2() is a runtime check performed using CPUID
290 /// \note This function is only available on Intel IA-32 platforms
291 inline bool HasPadlockACE2()
292 {
293 if (!g_x86DetectionDone)
294 DetectX86Features();
295 return g_hasPadlockACE2;
296 }
297
298 /// \brief Determines Padlock PHE availability
299 /// \returns true if VIA Padlock PHE is determined to be available, false otherwise
300 /// \details HasPadlockPHE() is a runtime check performed using CPUID
301 /// \note This function is only available on Intel IA-32 platforms
302 inline bool HasPadlockPHE()
303 {
304 if (!g_x86DetectionDone)
305 DetectX86Features();
306 return g_hasPadlockPHE;
307 }
308
309 /// \brief Determines Padlock PMM availability
310 /// \returns true if VIA Padlock PMM is determined to be available, false otherwise
311 /// \details HasPadlockPMM() is a runtime check performed using CPUID
312 /// \note This function is only available on Intel IA-32 platforms
313 inline bool HasPadlockPMM()
314 {
315 if (!g_x86DetectionDone)
316 DetectX86Features();
317 return g_hasPadlockPMM;
318 }
319
320 /// \brief Provides the cache line size
321 /// \returns lower bound on the size of a cache line in bytes, if available
322 /// \details GetCacheLineSize() returns the lower bound on the size of a cache line, if it
323 /// is available. If the value is not available at runtime, then 32 is returned for a 32-bit
324 /// processor and 64 is returned for a 64-bit processor.
325 /// \details x86/x32/x64 uses CPUID to determine the value and it is usually accurate. PowerPC
326 /// and AIX also makes the value available to user space and it is also usually accurate. The
327 /// ARM processor equivalent is a privileged instruction, so a compile time value is returned.
328 inline int GetCacheLineSize()
329 {
330 if (!g_x86DetectionDone)
331 DetectX86Features();
332 return g_cacheLineSize;
333 }
334 //@}
335
336 #endif // CRYPTOPP_BOOL_X86 || CRYPTOPP_BOOL_X32 || CRYPTOPP_BOOL_X64
337
338 // ***************************** ARM-32, Aarch32 and Aarch64 ***************************** //
339
340 #if CRYPTOPP_BOOL_ARM32 || CRYPTOPP_BOOL_ARMV8 || CRYPTOPP_DOXYGEN_PROCESSING
341
342 // Hide from Doxygen
343 #ifndef CRYPTOPP_DOXYGEN_PROCESSING
344 extern bool g_ArmDetectionDone;
345 extern bool g_hasARMv7;
346 extern bool g_hasNEON;
347 extern bool g_hasPMULL;
348 extern bool g_hasCRC32;
349 extern bool g_hasAES;
350 extern bool g_hasSHA1;
351 extern bool g_hasSHA2;
352 extern bool g_hasSHA512;
353 extern bool g_hasSHA3;
354 extern bool g_hasSM3;
355 extern bool g_hasSM4;
356 void CRYPTOPP_API DetectArmFeatures();
357 #endif // CRYPTOPP_DOXYGEN_PROCESSING
358
359 /// \name ARM A-32, Aarch32 and AArch64 CPU FEATURES
360 //@{
361
362 /// \brief Determine if an ARM processor is ARMv7 or above
363 /// \returns true if the hardware is ARMv7 or above, false otherwise.
364 /// \details Some AES code requires ARMv7 or above
365 /// \since Crypto++ 7.1
366 /// \note This function is only available on ARM-32, Aarch32 and Aarch64 platforms
367 inline bool HasARMv7()
368 {
369 // ASIMD is a core feature on Aarch32 and Aarch64 like SSE2 is a core feature on x86_64
370 #if defined(__aarch32__) || defined(__aarch64__)
371 return true;
372 #else
373 if (!g_ArmDetectionDone)
374 DetectArmFeatures();
375 return g_hasARMv7;
376 #endif
377 }
378
379 /// \brief Determine if an ARM processor has Advanced SIMD available
380 /// \returns true if the hardware is capable of Advanced SIMD at runtime, false otherwise.
381 /// \details Advanced SIMD instructions are available under most ARMv7, Aarch32 and Aarch64.
382 /// \details Runtime support requires compile time support. When compiling with GCC, you may
383 /// need to compile with <tt>-mfpu=neon</tt> (32-bit) or <tt>-march=armv8-a</tt>
384 /// (64-bit). Also see ARM's <tt>__ARM_NEON</tt> preprocessor macro.
385 /// \since Crypto++ 5.6.4
386 /// \note This function is only available on ARM-32, Aarch32 and Aarch64 platforms
387 inline bool HasNEON()
388 {
389 // ASIMD is a core feature on Aarch32 and Aarch64 like SSE2 is a core feature on x86_64
390 #if defined(__aarch32__) || defined(__aarch64__)
391 return true;
392 #else
393 if (!g_ArmDetectionDone)
394 DetectArmFeatures();
395 return g_hasNEON;
396 #endif
397 }
398
399 /// \brief Determine if an ARM processor provides Polynomial Multiplication
400 /// \returns true if the hardware is capable of polynomial multiplications at runtime,
401 /// false otherwise.
402 /// \details The multiplication instructions are available under Aarch32 and Aarch64.
403 /// \details Runtime support requires compile time support. When compiling with GCC,
404 /// you may need to compile with <tt>-march=armv8-a+crypto</tt>; while Apple requires
405 /// <tt>-arch arm64</tt>. Also see ARM's <tt>__ARM_FEATURE_CRYPTO</tt> preprocessor macro.
406 /// \since Crypto++ 5.6.4
407 /// \note This function is only available on Aarch32 and Aarch64 platforms
408 inline bool HasPMULL()
409 {
410 #if defined(__aarch32__) || defined(__aarch64__)
411 if (!g_ArmDetectionDone)
412 DetectArmFeatures();
413 return g_hasPMULL;
414 #else
415 return false;
416 #endif
417 }
418
419 /// \brief Determine if an ARM processor has CRC32 available
420 /// \returns true if the hardware is capable of CRC32 at runtime, false otherwise.
421 /// \details CRC32 instructions provide access to the processor's CRC-32 and CRC-32C
422 /// instructions. They are provided by ARM C Language Extensions 2.0 (ACLE 2.0) and
423 /// available under Aarch32 and Aarch64.
424 /// \details Runtime support requires compile time support. When compiling with GCC,
425 /// you may need to compile with <tt>-march=armv8-a+crc</tt>; while Apple requires
426 /// <tt>-arch arm64</tt>. Also see ARM's <tt>__ARM_FEATURE_CRC32</tt> preprocessor macro.
427 /// \since Crypto++ 5.6.4
428 /// \note This function is only available on Aarch32 and Aarch64 platforms
429 inline bool HasCRC32()
430 {
431 #if defined(__aarch32__) || defined(__aarch64__)
432 if (!g_ArmDetectionDone)
433 DetectArmFeatures();
434 return g_hasCRC32;
435 #else
436 return false;
437 #endif
438 }
439
440 /// \brief Determine if an ARM processor has AES available
441 /// \returns true if the hardware is capable of AES at runtime, false otherwise.
442 /// \details AES is part of the optional Crypto extensions on Aarch32 and Aarch64. They are
443 /// accessed using ARM C Language Extensions 2.0 (ACLE 2.0).
444 /// \details Runtime support requires compile time support. When compiling with GCC, you may
445 /// need to compile with <tt>-march=armv8-a+crypto</tt>; while Apple requires
446 /// <tt>-arch arm64</tt>. Also see ARM's <tt>__ARM_FEATURE_CRYPTO</tt> preprocessor macro.
447 /// \since Crypto++ 5.6.4
448 /// \note This function is only available on Aarch32 and Aarch64 platforms
449 inline bool HasAES()
450 {
451 #if defined(__aarch32__) || defined(__aarch64__)
452 if (!g_ArmDetectionDone)
453 DetectArmFeatures();
454 return g_hasAES;
455 #else
456 return false;
457 #endif
458 }
459
460 /// \brief Determine if an ARM processor has SHA1 available
461 /// \returns true if the hardware is capable of SHA1 at runtime, false otherwise.
462 /// \details SHA1 is part of the optional Crypto extensions on Aarch32 and Aarch64. They are
463 /// accessed using ARM C Language Extensions 2.0 (ACLE 2.0).
464 /// \details Runtime support requires compile time support. When compiling with GCC, you may
465 /// need to compile with <tt>-march=armv8-a+crypto</tt>; while Apple requires
466 /// <tt>-arch arm64</tt>. Also see ARM's <tt>__ARM_FEATURE_CRYPTO</tt> preprocessor macro.
467 /// \since Crypto++ 5.6.4
468 /// \note This function is only available on Aarch32 and Aarch64 platforms
469 inline bool HasSHA1()
470 {
471 #if defined(__aarch32__) || defined(__aarch64__)
472 if (!g_ArmDetectionDone)
473 DetectArmFeatures();
474 return g_hasSHA1;
475 #else
476 return false;
477 #endif
478 }
479
480 /// \brief Determine if an ARM processor has SHA256 available
481 /// \returns true if the hardware is capable of SHA256 at runtime, false otherwise.
482 /// \details SHA256 is part of the optional Crypto extensions on Aarch32 and Aarch64. They are
483 /// accessed using ARM C Language Extensions 2.0 (ACLE 2.0).
484 /// \details Runtime support requires compile time support. When compiling with GCC, you may
485 /// need to compile with <tt>-march=armv8-a+crypto</tt>; while Apple requires
486 /// <tt>-arch arm64</tt>. Also see ARM's <tt>__ARM_FEATURE_CRYPTO</tt> preprocessor macro.
487 /// \since Crypto++ 5.6.4
488 /// \note This function is only available on Aarch32 and Aarch64 platforms
489 inline bool HasSHA2()
490 {
491 #if defined(__aarch32__) || defined(__aarch64__)
492 if (!g_ArmDetectionDone)
493 DetectArmFeatures();
494 return g_hasSHA2;
495 #else
496 return false;
497 #endif
498 }
499
500 /// \brief Determine if an ARM processor has SHA512 available
501 /// \returns true if the hardware is capable of SHA512 at runtime, false otherwise.
502 /// \details SHA512 is part of the ARMv8.4 Crypto extensions on Aarch32 and Aarch64. They
503 /// are accessed using ARM C Language Extensions 2.0 (ACLE 2.0).
504 /// \details Runtime support requires compile time support. When compiling with GCC, you
505 /// may need to compile with <tt>-march=armv8.4-a+crypto</tt>; while Apple requires
506 /// <tt>-arch arm64</tt>. Also see ARM's <tt>__ARM_FEATURE_CRYPTO</tt> preprocessor macro.
507 /// \since Crypto++ 7.1
508 /// \note This function is only available on Aarch32 and Aarch64 platforms
509 inline bool HasSHA512()
510 {
511 #if defined(__aarch32__) || defined(__aarch64__)
512 if (!g_ArmDetectionDone)
513 DetectArmFeatures();
514 return g_hasSHA512;
515 #else
516 return false;
517 #endif
518 }
519
520 /// \brief Determine if an ARM processor has SHA3 available
521 /// \returns true if the hardware is capable of SHA3 at runtime, false otherwise.
522 /// \details SHA3 is part of the ARMv8.4 Crypto extensions on Aarch32 and Aarch64. They
523 /// are accessed using ARM C Language Extensions 2.0 (ACLE 2.0).
524 /// \details Runtime support requires compile time support. When compiling with GCC, you
525 /// may need to compile with <tt>-march=armv8.4-a+crypto</tt>; while Apple requires
526 /// <tt>-arch arm64</tt>. Also see ARM's <tt>__ARM_FEATURE_CRYPTO</tt> preprocessor macro.
527 /// \since Crypto++ 7.1
528 /// \note This function is only available on Aarch32 and Aarch64 platforms
529 inline bool HasSHA3()
530 {
531 #if defined(__aarch32__) || defined(__aarch64__)
532 if (!g_ArmDetectionDone)
533 DetectArmFeatures();
534 return g_hasSHA3;
535 #else
536 return false;
537 #endif
538 }
539
540 /// \brief Determine if an ARM processor has SM3 available
541 /// \returns true if the hardware is capable of SM3 at runtime, false otherwise.
542 /// \details SM3 is part of the ARMv8.4 Crypto extensions on Aarch32 and Aarch64. They
543 /// are accessed using ARM C Language Extensions 2.0 (ACLE 2.0).
544 /// \details Runtime support requires compile time support. When compiling with GCC, you
545 /// may need to compile with <tt>-march=armv8.4-a+crypto</tt>; while Apple requires
546 /// <tt>-arch arm64</tt>. Also see ARM's <tt>__ARM_FEATURE_CRYPTO</tt> preprocessor macro.
547 /// \since Crypto++ 7.1
548 /// \note This function is only available on Aarch32 and Aarch64 platforms
549 inline bool HasSM3()
550 {
551 #if defined(__aarch32__) || defined(__aarch64__)
552 if (!g_ArmDetectionDone)
553 DetectArmFeatures();
554 return g_hasSM3;
555 #else
556 return false;
557 #endif
558 }
559
560 /// \brief Determine if an ARM processor has SM4 available
561 /// \returns true if the hardware is capable of SM4 at runtime, false otherwise.
562 /// \details SM4 is part of the ARMv8.4 Crypto extensions on Aarch32 and Aarch64. They
563 /// are accessed using ARM C Language Extensions 2.0 (ACLE 2.0).
564 /// \details Runtime support requires compile time support. When compiling with GCC, you
565 /// may need to compile with <tt>-march=armv8.4-a+crypto</tt>; while Apple requires
566 /// <tt>-arch arm64</tt>. Also see ARM's <tt>__ARM_FEATURE_CRYPTO</tt> preprocessor macro.
567 /// \since Crypto++ 7.1
568 /// \note This function is only available on Aarch32 and Aarch64 platforms
569 inline bool HasSM4()
570 {
571 #if defined(__aarch32__) || defined(__aarch64__)
572 if (!g_ArmDetectionDone)
573 DetectArmFeatures();
574 return g_hasSM4;
575 #else
576 return false;
577 #endif
578 }
579
580 //@}
581
582 #endif // CRYPTOPP_BOOL_ARM32 || CRYPTOPP_BOOL_ARMV8
583
584 // ***************************** PowerPC ***************************** //
585
586 #if CRYPTOPP_BOOL_PPC32 || CRYPTOPP_BOOL_PPC64 || CRYPTOPP_DOXYGEN_PROCESSING
587
588 // Hide from Doxygen
589 #ifndef CRYPTOPP_DOXYGEN_PROCESSING
590 extern bool g_PowerpcDetectionDone;
591 extern bool g_hasAltivec;
592 extern bool g_hasPower7;
593 extern bool g_hasPower8;
594 extern bool g_hasPower9;
595 extern bool g_hasAES;
596 extern bool g_hasPMULL;
597 extern bool g_hasSHA256;
598 extern bool g_hasSHA512;
599 extern bool g_hasDARN;
600 extern word32 g_cacheLineSize;
601 void CRYPTOPP_API DetectPowerpcFeatures();
602 #endif // CRYPTOPP_DOXYGEN_PROCESSING
603
604 /// \name POWERPC CPU FEATURES
605 //@{
606
607 /// \brief Determine if a PowerPC processor has Altivec available
608 /// \returns true if the hardware is capable of Altivec at runtime, false otherwise.
609 /// \details Altivec instructions are available on modern PowerPCs.
610 /// \details Runtime support requires compile time support. When compiling with GCC, you may
611 /// need to compile with <tt>-mcpu=power4</tt>; while IBM XL C/C++ compilers require
612 /// <tt>-qarch=pwr6 -qaltivec</tt>. Also see PowerPC's <tt>_ALTIVEC_</tt> preprocessor macro.
613 /// \note This function is only available on PowerPC and PowerPC-64 platforms
614 inline bool HasAltivec()
615 {
616 if (!g_PowerpcDetectionDone)
617 DetectPowerpcFeatures();
618 return g_hasAltivec;
619 }
620
621 /// \brief Determine if a PowerPC processor has Power7 available
622 /// \returns true if the hardware is capable of Power7 at runtime, false otherwise.
623 /// \details Runtime support requires compile time support. When compiling with GCC, you may
624 /// need to compile with <tt>-mcpu=power7</tt>; while IBM XL C/C++ compilers require
625 /// <tt>-qarch=pwr7 -qaltivec</tt>. Also see PowerPC's <tt>_ALTIVEC_</tt> preprocessor macro.
626 /// \note This function is only available on PowerPC and PowerPC-64 platforms
627 inline bool HasPower7()
628 {
629 if (!g_PowerpcDetectionDone)
630 DetectPowerpcFeatures();
631 return g_hasPower7;
632 }
633
634 /// \brief Determine if a PowerPC processor has Power8 available
635 /// \returns true if the hardware is capable of Power8 at runtime, false otherwise.
636 /// \details Runtime support requires compile time support. When compiling with GCC, you may
637 /// need to compile with <tt>-mcpu=power8</tt>; while IBM XL C/C++ compilers require
638 /// <tt>-qarch=pwr8 -qaltivec</tt>. Also see PowerPC's <tt>_ALTIVEC_</tt> preprocessor macro.
639 /// \note This function is only available on PowerPC and PowerPC-64 platforms
640 inline bool HasPower8()
641 {
642 if (!g_PowerpcDetectionDone)
643 DetectPowerpcFeatures();
644 return g_hasPower8;
645 }
646
647 /// \brief Determine if a PowerPC processor has Power9 available
648 /// \returns true if the hardware is capable of Power9 at runtime, false otherwise.
649 /// \details Runtime support requires compile time support. When compiling with GCC, you may
650 /// need to compile with <tt>-mcpu=power9</tt>; while IBM XL C/C++ compilers require
651 /// <tt>-qarch=pwr9 -qaltivec</tt>. Also see PowerPC's <tt>_ALTIVEC_</tt> preprocessor macro.
652 /// \note This function is only available on PowerPC and PowerPC-64 platforms
653 inline bool HasPower9()
654 {
655 if (!g_PowerpcDetectionDone)
656 DetectPowerpcFeatures();
657 return g_hasPower9;
658 }
659
660 /// \brief Determine if a PowerPC processor has AES available
661 /// \returns true if the hardware is capable of AES at runtime, false otherwise.
662 /// \details AES is part of the in-crypto extensions on Power8 and Power9.
663 /// \details Runtime support requires compile time support. When compiling with GCC, you may
664 /// need to compile with <tt>-mcpu=power8</tt>; while IBM XL C/C++ compilers require
665 /// <tt>-qarch=pwr8 -qaltivec</tt>. Also see PowerPC's <tt>__CRYPTO</tt> preprocessor macro.
666 /// \note This function is only available on PowerPC and PowerPC-64 platforms
667 inline bool HasAES()
668 {
669 if (!g_PowerpcDetectionDone)
670 DetectPowerpcFeatures();
671 return g_hasAES;
672 }
673
674 /// \brief Determine if a PowerPC processor has Polynomial Multiply available
675 /// \returns true if the hardware is capable of PMULL at runtime, false otherwise.
676 /// \details PMULL is part of the in-crypto extensions on Power8 and Power9.
677 /// \details Runtime support requires compile time support. When compiling with GCC, you may
678 /// need to compile with <tt>-mcpu=power8</tt>; while IBM XL C/C++ compilers require
679 /// <tt>-qarch=pwr8 -qaltivec</tt>. Also see PowerPC's <tt>__CRYPTO</tt> preprocessor macro.
680 /// \note This function is only available on PowerPC and PowerPC-64 platforms
681 inline bool HasPMULL()
682 {
683 if (!g_PowerpcDetectionDone)
684 DetectPowerpcFeatures();
685 return g_hasPMULL;
686 }
687
688 /// \brief Determine if a PowerPC processor has SHA256 available
689 /// \returns true if the hardware is capable of SHA256 at runtime, false otherwise.
690 /// \details SHA is part of the in-crypto extensions on Power8 and Power9.
691 /// \details Runtime support requires compile time support. When compiling with GCC, you may
692 /// need to compile with <tt>-mcpu=power8</tt>; while IBM XL C/C++ compilers require
693 /// <tt>-qarch=pwr8 -qaltivec</tt>. Also see PowerPC's <tt>__CRYPTO</tt> preprocessor macro.
694 /// \note This function is only available on PowerPC and PowerPC-64 platforms
695 inline bool HasSHA256()
696 {
697 if (!g_PowerpcDetectionDone)
698 DetectPowerpcFeatures();
699 return g_hasSHA256;
700 }
701
702 /// \brief Determine if a PowerPC processor has SHA512 available
703 /// \returns true if the hardware is capable of SHA512 at runtime, false otherwise.
704 /// \details SHA is part of the in-crypto extensions on Power8 and Power9.
705 /// \details Runtime support requires compile time support. When compiling with GCC, you may
706 /// need to compile with <tt>-mcpu=power8</tt>; while IBM XL C/C++ compilers require
707 /// <tt>-qarch=pwr8 -qaltivec</tt>. Also see PowerPC's <tt>__CRYPTO</tt> preprocessor macro.
708 /// \note This function is only available on PowerPC and PowerPC-64 platforms
709 inline bool HasSHA512()
710 {
711 if (!g_PowerpcDetectionDone)
712 DetectPowerpcFeatures();
713 return g_hasSHA512;
714 }
715
716 /// \brief Determine if a PowerPC processor has DARN available
717 /// \returns true if the hardware is capable of DARN at runtime, false otherwise.
718 /// \details Runtime support requires compile time support. When compiling with GCC, you may
719 /// need to compile with <tt>-mcpu=power9</tt>; while IBM XL C/C++ compilers require
720 /// <tt>-qarch=pwr9 -qaltivec</tt>. Also see PowerPC's <tt>_ALTIVEC_</tt> preprocessor macro.
721 /// \note This function is only available on PowerPC and PowerPC-64 platforms
722 inline bool HasDARN()
723 {
724 if (!g_PowerpcDetectionDone)
725 DetectPowerpcFeatures();
726
727 // see comments in cpu.cpp
728 #if defined(__ibmxl__) && defined(__linux__)
729 return false;
730 #else
731 return g_hasDARN;
732 #endif
733 }
734
735 /// \brief Provides the cache line size
736 /// \returns lower bound on the size of a cache line in bytes, if available
737 /// \details GetCacheLineSize() returns the lower bound on the size of a cache line, if it
738 /// is available. If the value is not available at runtime, then 32 is returned for a 32-bit
739 /// processor and 64 is returned for a 64-bit processor.
740 /// \details x86/x32/x64 uses CPUID to determine the value and it is usually accurate. PowerPC
741 /// and AIX also makes the value available to user space and it is also usually accurate. The
742 /// ARM processor equivalent is a privileged instruction, so a compile time value is returned.
743 inline int GetCacheLineSize()
744 {
745 if (!g_PowerpcDetectionDone)
746 DetectPowerpcFeatures();
747 return g_cacheLineSize;
748 }
749
750 //@}
751
752 #endif // CRYPTOPP_BOOL_PPC32 || CRYPTOPP_BOOL_PPC64
753
754 // ***************************** L1 cache line ***************************** //
755
756 // Non-Intel systems
757 #if !(CRYPTOPP_BOOL_X86 || CRYPTOPP_BOOL_X32 || CRYPTOPP_BOOL_X64 || CRYPTOPP_BOOL_PPC32 || CRYPTOPP_BOOL_PPC64)
758 /// \brief Provides the cache line size
759 /// \returns lower bound on the size of a cache line in bytes, if available
760 /// \details GetCacheLineSize() returns the lower bound on the size of a cache line, if it
761 /// is available. If the value is not available at runtime, then 32 is returned for a 32-bit
762 /// processor and 64 is returned for a 64-bit processor.
763 /// \details x86/x32/x64 uses CPUID to determine the value and it is usually accurate. PowerPC
764 /// and AIX also makes the value available to user space and it is also usually accurate. The
765 /// ARM processor equivalent is a privileged instruction, so a compile time value is returned.
766 inline int GetCacheLineSize()
767 {
768 return CRYPTOPP_L1_CACHE_LINE_SIZE;
769 }
770 #endif // Non-Intel systems
771
772 #endif // CRYPTOPP_GENERATE_X64_MASM
773
774 // ***************************** Inline ASM Helper ***************************** //
775
776 #ifndef CRYPTOPP_DOXYGEN_PROCESSING
777
778 #if CRYPTOPP_BOOL_X86 || CRYPTOPP_BOOL_X32 || CRYPTOPP_BOOL_X64
779
780 #ifdef CRYPTOPP_GENERATE_X64_MASM
781 #define AS1(x) x*newline*
782 #define AS2(x, y) x, y*newline*
783 #define AS3(x, y, z) x, y, z*newline*
784 #define ASS(x, y, a, b, c, d) x, y, a*64+b*16+c*4+d*newline*
785 #define ASL(x) label##x:*newline*
786 #define ASJ(x, y, z) x label##y*newline*
787 #define ASC(x, y) x label##y*newline*
788 #define AS_HEX(y) 0##y##h
789 #elif defined(_MSC_VER) || defined(__BORLANDC__)
790 #define AS1(x) __asm {x}
791 #define AS2(x, y) __asm {x, y}
792 #define AS3(x, y, z) __asm {x, y, z}
793 #define ASS(x, y, a, b, c, d) __asm {x, y, (a)*64+(b)*16+(c)*4+(d)}
794 #define ASL(x) __asm {label##x:}
795 #define ASJ(x, y, z) __asm {x label##y}
796 #define ASC(x, y) __asm {x label##y}
797 #define CRYPTOPP_NAKED __declspec(naked)
798 #define AS_HEX(y) 0x##y
799 #else
800 // define these in two steps to allow arguments to be expanded
801 #define GNU_AS1(x) #x ";" NEW_LINE
802 #define GNU_AS2(x, y) #x ", " #y ";" NEW_LINE
803 #define GNU_AS3(x, y, z) #x ", " #y ", " #z ";" NEW_LINE
804 #define GNU_ASL(x) "\n" #x ":" NEW_LINE
805 // clang 5.0.0 and apple clang 9.0.0 don't support numerical backward jumps
806 #if (CRYPTOPP_LLVM_CLANG_VERSION >= 50000) || (CRYPTOPP_APPLE_CLANG_VERSION >= 90000)
807 #define GNU_ASJ(x, y, z) ATT_PREFIX ";" NEW_LINE #x " " #y #z ";" NEW_LINE INTEL_PREFIX ";" NEW_LINE
808 #else
809 #define GNU_ASJ(x, y, z) #x " " #y #z ";" NEW_LINE
810 #endif
811 #define AS1(x) GNU_AS1(x)
812 #define AS2(x, y) GNU_AS2(x, y)
813 #define AS3(x, y, z) GNU_AS3(x, y, z)
814 #define ASS(x, y, a, b, c, d) #x ", " #y ", " #a "*64+" #b "*16+" #c "*4+" #d ";"
815 #define ASL(x) GNU_ASL(x)
816 #define ASJ(x, y, z) GNU_ASJ(x, y, z)
817 #define ASC(x, y) #x " " #y ";"
818 #define CRYPTOPP_NAKED
819 #define AS_HEX(y) 0x##y
820 #endif
821
822 #define IF0(y)
823 #define IF1(y) y
824
825 #ifdef CRYPTOPP_GENERATE_X64_MASM
826 #define ASM_MOD(x, y) ((x) MOD (y))
827 #define XMMWORD_PTR XMMWORD PTR
828 #else
829 // GNU assembler doesn't seem to have mod operator
830 #define ASM_MOD(x, y) ((x)-((x)/(y))*(y))
831 // GAS 2.15 doesn't support XMMWORD PTR. it seems necessary only for MASM
832 #define XMMWORD_PTR
833 #endif
834
835 #if CRYPTOPP_BOOL_X86
836 #define AS_REG_1 ecx
837 #define AS_REG_2 edx
838 #define AS_REG_3 esi
839 #define AS_REG_4 edi
840 #define AS_REG_5 eax
841 #define AS_REG_6 ebx
842 #define AS_REG_7 ebp
843 #define AS_REG_1d ecx
844 #define AS_REG_2d edx
845 #define AS_REG_3d esi
846 #define AS_REG_4d edi
847 #define AS_REG_5d eax
848 #define AS_REG_6d ebx
849 #define AS_REG_7d ebp
850 #define WORD_SZ 4
851 #define WORD_REG(x) e##x
852 #define WORD_PTR DWORD PTR
853 #define AS_PUSH_IF86(x) AS1(push e##x)
854 #define AS_POP_IF86(x) AS1(pop e##x)
855 #define AS_JCXZ jecxz
856 #elif CRYPTOPP_BOOL_X32
857 #define AS_REG_1 ecx
858 #define AS_REG_2 edx
859 #define AS_REG_3 r8d
860 #define AS_REG_4 r9d
861 #define AS_REG_5 eax
862 #define AS_REG_6 r10d
863 #define AS_REG_7 r11d
864 #define AS_REG_1d ecx
865 #define AS_REG_2d edx
866 #define AS_REG_3d r8d
867 #define AS_REG_4d r9d
868 #define AS_REG_5d eax
869 #define AS_REG_6d r10d
870 #define AS_REG_7d r11d
871 #define WORD_SZ 4
872 #define WORD_REG(x) e##x
873 #define WORD_PTR DWORD PTR
874 #define AS_PUSH_IF86(x) AS1(push r##x)
875 #define AS_POP_IF86(x) AS1(pop r##x)
876 #define AS_JCXZ jecxz
877 #elif CRYPTOPP_BOOL_X64
878 #ifdef CRYPTOPP_GENERATE_X64_MASM
879 #define AS_REG_1 rcx
880 #define AS_REG_2 rdx
881 #define AS_REG_3 r8
882 #define AS_REG_4 r9
883 #define AS_REG_5 rax
884 #define AS_REG_6 r10
885 #define AS_REG_7 r11
886 #define AS_REG_1d ecx
887 #define AS_REG_2d edx
888 #define AS_REG_3d r8d
889 #define AS_REG_4d r9d
890 #define AS_REG_5d eax
891 #define AS_REG_6d r10d
892 #define AS_REG_7d r11d
893 #else
894 #define AS_REG_1 rdi
895 #define AS_REG_2 rsi
896 #define AS_REG_3 rdx
897 #define AS_REG_4 rcx
898 #define AS_REG_5 r8
899 #define AS_REG_6 r9
900 #define AS_REG_7 r10
901 #define AS_REG_1d edi
902 #define AS_REG_2d esi
903 #define AS_REG_3d edx
904 #define AS_REG_4d ecx
905 #define AS_REG_5d r8d
906 #define AS_REG_6d r9d
907 #define AS_REG_7d r10d
908 #endif
909 #define WORD_SZ 8
910 #define WORD_REG(x) r##x
911 #define WORD_PTR QWORD PTR
912 #define AS_PUSH_IF86(x)
913 #define AS_POP_IF86(x)
914 #define AS_JCXZ jrcxz
915 #endif
916
917 // helper macro for stream cipher output
918 #define AS_XMM_OUTPUT4(labelPrefix, inputPtr, outputPtr, x0, x1, x2, x3, t, p0, p1, p2, p3, increment)\
919 AS2( test inputPtr, inputPtr)\
920 ASC( jz, labelPrefix##3)\
921 AS2( test inputPtr, 15)\
922 ASC( jnz, labelPrefix##7)\
923 AS2( pxor xmm##x0, [inputPtr+p0*16])\
924 AS2( pxor xmm##x1, [inputPtr+p1*16])\
925 AS2( pxor xmm##x2, [inputPtr+p2*16])\
926 AS2( pxor xmm##x3, [inputPtr+p3*16])\
927 AS2( add inputPtr, increment*16)\
928 ASC( jmp, labelPrefix##3)\
929 ASL(labelPrefix##7)\
930 AS2( movdqu xmm##t, [inputPtr+p0*16])\
931 AS2( pxor xmm##x0, xmm##t)\
932 AS2( movdqu xmm##t, [inputPtr+p1*16])\
933 AS2( pxor xmm##x1, xmm##t)\
934 AS2( movdqu xmm##t, [inputPtr+p2*16])\
935 AS2( pxor xmm##x2, xmm##t)\
936 AS2( movdqu xmm##t, [inputPtr+p3*16])\
937 AS2( pxor xmm##x3, xmm##t)\
938 AS2( add inputPtr, increment*16)\
939 ASL(labelPrefix##3)\
940 AS2( test outputPtr, 15)\
941 ASC( jnz, labelPrefix##8)\
942 AS2( movdqa [outputPtr+p0*16], xmm##x0)\
943 AS2( movdqa [outputPtr+p1*16], xmm##x1)\
944 AS2( movdqa [outputPtr+p2*16], xmm##x2)\
945 AS2( movdqa [outputPtr+p3*16], xmm##x3)\
946 ASC( jmp, labelPrefix##9)\
947 ASL(labelPrefix##8)\
948 AS2( movdqu [outputPtr+p0*16], xmm##x0)\
949 AS2( movdqu [outputPtr+p1*16], xmm##x1)\
950 AS2( movdqu [outputPtr+p2*16], xmm##x2)\
951 AS2( movdqu [outputPtr+p3*16], xmm##x3)\
952 ASL(labelPrefix##9)\
953 AS2( add outputPtr, increment*16)
954
955 #endif // CRYPTOPP_BOOL_X86 || CRYPTOPP_BOOL_X32 || CRYPTOPP_BOOL_X64
956
957 #endif // Not CRYPTOPP_DOXYGEN_PROCESSING
958
959 NAMESPACE_END
960
961 // Issue 340
962 #if CRYPTOPP_GCC_DIAGNOSTIC_AVAILABLE
963 # pragma GCC diagnostic pop
964 #endif
965
966 #endif // CRYPTOPP_CPU_H
HasSHA
bool HasSHA()
Determines SHA availability.
Definition: cpu.h:189
HasDARN
bool HasDARN()
Determine if a PowerPC processor has DARN available.
Definition: cpu.h:722
HasAltivec
bool HasAltivec()
Determine if a PowerPC processor has Altivec available.
Definition: cpu.h:614
HasSM4
bool HasSM4()
Determine if an ARM processor has SM4 available.
Definition: cpu.h:569
HasCRC32
bool HasCRC32()
Determine if an ARM processor has CRC32 available.
Definition: cpu.h:429
HasSSSE3
bool HasSSSE3()
Determines SSSE3 availability.
Definition: cpu.h:131
HasADX
bool HasADX()
Determines ADX availability.
Definition: cpu.h:201
HasPadlockRNG
bool HasPadlockRNG()
Determines Padlock RNG availability.
Definition: cpu.h:269
HasAVX2
bool HasAVX2()
Determines AVX2 availability.
Definition: cpu.h:225
HasAES
bool HasAES()
Determine if an ARM processor has AES available.
Definition: cpu.h:449
IsP4
bool IsP4()
Determines if the CPU is an Intel P4.
Definition: cpu.h:236
config.h
Library configuration file.
GetCacheLineSize
int GetCacheLineSize()
Provides the cache line size.
Definition: cpu.h:328
HasRDRAND
bool HasRDRAND()
Determines RDRAND availability.
Definition: cpu.h:247
HasPower7
bool HasPower7()
Determine if a PowerPC processor has Power7 available.
Definition: cpu.h:627
HasSHA256
bool HasSHA256()
Determine if a PowerPC processor has SHA256 available.
Definition: cpu.h:695
HasSM3
bool HasSM3()
Determine if an ARM processor has SM3 available.
Definition: cpu.h:549
HasPower8
bool HasPower8()
Determine if a PowerPC processor has Power8 available.
Definition: cpu.h:640
HasRDSEED
bool HasRDSEED()
Determines RDSEED availability.
Definition: cpu.h:258
HasCLMUL
bool HasCLMUL()
Determines Carryless Multiply availability.
Definition: cpu.h:177
HasSHA1
bool HasSHA1()
Determine if an ARM processor has SHA1 available.
Definition: cpu.h:469
HasSHA512
bool HasSHA512()
Determine if an ARM processor has SHA512 available.
Definition: cpu.h:509
HasPadlockACE2
bool HasPadlockACE2()
Determines Padlock ACE2 availability.
Definition: cpu.h:291
HasPadlockPHE
bool HasPadlockPHE()
Determines Padlock PHE availability.
Definition: cpu.h:302
HasPadlockPMM
bool HasPadlockPMM()
Determines Padlock PMM availability.
Definition: cpu.h:313
HasAESNI
bool HasAESNI()
Determines AES-NI availability.
Definition: cpu.h:165
HasPower9
bool HasPower9()
Determine if a PowerPC processor has Power9 available.
Definition: cpu.h:653
HasSSE2
bool HasSSE2()
Determines SSE2 availability.
Definition: cpu.h:116
HasSHA2
bool HasSHA2()
Determine if an ARM processor has SHA256 available.
Definition: cpu.h:489
HasAVX
bool HasAVX()
Determines AVX availability.
Definition: cpu.h:213
HasSSE41
bool HasSSE41()
Determines SSE4.1 availability.
Definition: cpu.h:142
CryptoPP
Crypto++ library namespace.
HasSHA3
bool HasSHA3()
Determine if an ARM processor has SHA3 available.
Definition: cpu.h:529
HasARMv7
bool HasARMv7()
Determine if an ARM processor is ARMv7 or above.
Definition: cpu.h:367
HasPadlockACE
bool HasPadlockACE()
Determines Padlock ACE availability.
Definition: cpu.h:280
HasSSE42
bool HasSSE42()
Determines SSE4.2 availability.
Definition: cpu.h:153
HasPMULL
bool HasPMULL()
Determine if an ARM processor provides Polynomial Multiplication.
Definition: cpu.h:408
HasNEON
bool HasNEON()
Determine if an ARM processor has Advanced SIMD available.
Definition: cpu.h:387